1. Field of the Invention
The present invention relates to a voltage comparing circuit, particularly to a voltage comparing circuit of a chopper type used in a high-speed A/D converter or the like.
2. Description of the Prior Art
Conventionally, the inventors of the application have proposed a voltage comparing circuit of a chopper type using an inverter in Japanese Patent No. 3105862. An explanation will be given of the voltage comparing circuit of the publication in reference to FIG. 7 through FIG. 10 as follows. FIG. 7 shows the voltage comparing circuit of the publication and FIGS. 8A through 8C respectively show operational states in an input sampling mode, an amplifying mode and a latch mode of the voltage comparing circuit of FIG. 7. Further, FIG. 9 is a time chart showing operation of respective switches in the respective modes. In the drawings, numerals 101 through 108 designate switches, numerals 110, 111, 114 and 115 designate capacitors and numerals 112 and 113 designate inverters. Further, notation Vip designates positive side voltage of an analog input signal, notation Vin designates negative side voltage of the analog input signal, notation Vrp designates positive side voltage of reference voltage and notation Vrn designates negative side voltage of the reference voltage.
First, in the case of input sampling mode, as shown by FIG. 8A and FIG. 9, the switches 101, 102, 105, 106, 107 and 108 are made ON and the switches 103 and 104 are made OFF. Thereby, a difference between the positive side voltage Vip of the analog input signal and logical threshold voltage VLT112 of the inverter 112, is stored in the capacitor 110 and a difference between the negative side voltage Vin of the analog input signal and logical threshold voltage VLT113 of the inverter 113, is stored in the capacitor 111.
In the amplifying mode, as shown by FIG. 8B and FIG. 9, the switches 103 and 104 are made ON and the switches 101, 102, 105, 106, 107 and 108 are made OFF. Thereby, the inverter 112 amplifies a difference between the positive side voltage Vip of the analog input signal and the positive side voltage Vrp of the reference voltage and the inverter 113 amplifies a difference between the negative side voltage Vin of the analog input signal and the negative side voltage Vrn of the reference voltage to thereby respectively generate outputs Vo1 and Vo2.
Next, when the latch mode is brought about, as shown by FIG. 8C and FIG. 9, the switches 103, 104, 107 and 108 are made ON and the switches 101, 102, 105 and 106 are made OFF. Thereby, the inverters 112 and 113 operate as flip-flop since positive feedback is applied thereon via the capacitors 114 and 115. At this occasion, there is enlarged unbalance of output amplitudes of the inverters 112 and 113 produced by the difference between the positive side voltage Vip of the analog input signal and the positive side voltage Vrp of the reference voltage and the difference between the negative side voltage Vin of the analog input signal and the negative side voltage Vrn of the reference voltage, finally, in a transfer characteristic of input voltage Vin and output voltage Vout of the inverter shown in FIG. 10, the output voltage of one of the inverters is changed up to point A near to power source voltage VDD, the output voltage of other of the inverters is changed up to point C near to ground voltage VE and large or small between the analog input signal and the reference voltage is determined.
In this case, when electrostatic capacitance of the capacitor 110 is designated by notation C110, electric charge stored to the capacitor 110 is designated by notation QC110, electrostatic capacitance of the capacitor 111 is designated by notation C111 and electric charge stored to the capacitor 111 is designated by notation QC111, electric charged stored to the respective capacitors in the sampling mode is as shown below.
QC110=C110(Vipxe2x88x92VLT112)xe2x80x83xe2x80x83(1) 
QC111=C111(Vinxe2x88x92VLT113)xe2x80x83xe2x80x83(2) 
where notations VLT112 and VLT113 respectively designate logical threshold voltages of the inverters 112 and 113.
Further, when voltage at an input terminal of the inverter 112 is designated by notation Vg112 and voltage at an input terminal of the inverter 113 is designated by notation Vg113, since the electric charge stored to the capacitor in the sampling mode is preserved also in the amplifying mode, the voltages at the input terminals of the respective inverters in the amplifying mode are as shown below.                                                         Vg112              =                              Vrp                -                                  (                                      Vip                    -                    VLT112                                    )                                                                                                        =                                                (                                      Vrp                    -                    Vip                                    )                                +                VLT112                                                                        (        3        )                                                                    Vg113              =                              Vrn                -                                  (                                      Vin                    -                    VLT113                                    )                                                                                                        =                                                (                                      Vrn                    -                    Vin                                    )                                +                VLT113                                                                        (        4        )            
Further, when the positive side voltage Vip and the negative side voltage Vin of the analog input signal are represented by positive and negative analog input signals Vi with common mode voltage Vic of the analog input signal as a reference and the positive side voltage Vrp and the negative side voltage Vrn of the reference voltage are represented by positive and negative reference voltage Vr with common mode voltage Vrc of the reference voltage as a reference, the following relationships are established.
Vip=Vic+Vixe2x80x83xe2x80x83(5) 
Vin=Vicxe2x88x92Vixe2x80x83xe2x80x83(6) 
Vrp=Vrc+Vrxe2x80x83xe2x80x83(7) 
Vrn=Vrcxe2x88x92Vrxe2x80x83xe2x80x83(8) 
Hence, when Equations (5) through (8) are substituted for Equations (3) and (4), the following relationships are established.                                                         Vg112              =                                                (                                      Vrc                    +                    Vr                                    )                                -                                  (                                      Vic                    +                    Vi                                    )                                +                VLT112                                                                                        =                                                (                                      Vrc                    -                    Vic                                    )                                +                                  (                                      Vr                    -                    Vi                                    )                                +                VLT112                                                                        (        9        )                                                                    Vg113              =                                                (                                      Vrc                    -                    Vr                                    )                                -                                  (                                      Vic                    -                    Vi                                    )                                +                VLT113                                                                                        =                                                (                                      Vrc                    -                    Vic                                    )                                -                                  (                                      Vr                    -                    Vi                                    )                                +                VLT113                                                                        (        10        )            
When a difference between Vg112 and Vg113 is calculated, although a difference between the common mode voltage Vic of the analog input signal and the common mode voltage Vrc of the reference voltage is canceled, since in the amplifying mode, electric charge is not redistributed to the capacitor 110 and the capacitor 111, the input terminals of the inverters 112 and 113 are applied with a difference between the analog input signal Vi and the reference voltage Vr with the logical threshold voltages of the respective inverters as references and a difference between the common mode voltage Vic of the analog input signal and the common mode voltage Vrc of the reference voltage.
In this way, according to the conventional balance type voltage comparing circuit, the input terminal of the inverter is applied with even the difference between the common mode voltage of the analog input signal and the common mode voltage of the reference voltage other than the difference between the analog input signal and the reference voltage and therefore, when the difference between the common mode voltage of the analog input signal and the common mode voltage of the reference voltage is increased, the output of the inverter is saturated. Therefore, unbalance cannot be caused between the output voltages of the inverters 112 and 113 and in the latch mode, the large or small between the analog input signal Vi and the reference voltage Vr cannot be determined.
When the inverter used in the voltage comparing circuit is ideal having no restriction on the output amplitude, even when the difference between the common mode voltage of the analog input signal and the common mode voltage of the reference voltage is applied to the input of the inverter, the output is not saturated and therefore, in the latch mode, the difference between the outputs of the inverters can be amplified and large or small between the analog input signal and the reference voltage can normally be determined. However, according to the actual inverter, the output amplitude of the inverter is limited and therefore, when the difference between the common mode voltage of the analog input signal and the common mode voltage of the reference voltage is increased, the output of the inverter is saturated and the difference between the outputs of the inverters is nullified and therefore, there poses a problem that in the latch mode, large or small between the analog input signal and the reference voltage cannot normally be determined.
Object of the Invention
It is an object of the invention to provide a voltage comparing circuit capable of normally determining large or small between an analog input signal and reference voltage by canceling common mode voltages of the analog input signal and the reference voltage.
Summary of the Invention
A voltage comparing circuit of the invention includes a first and a second capacitor terminals on one side of which are respectively connected to a positive side voltage of an analog input signal and a negative side voltage of a reference voltage via a first and a second switch and terminals on other side of which are commonly connected, a third and a fourth capacitor terminals on one side of which are respectively connected to a positive side voltage of the reference voltage via a third and a fourth switch and a negative side voltage of the analog input signal and terminals on other side of which are commonly connected, a first and a second inverter respectively connected to a common connection terminal of the first and the second capacitors and a common connection terminal of the third and the fourth capacitors and connected with a fifth and a sixth switch respectively between input and output terminals thereof, a seventh and an eighth switch respectively connected between the input terminal of the first inverter and the output terminal of the second inverter and between the input terminal of the second inverter and the output terminal of the first inverter, and a ninth and a tenth switch respectively connected between the first capacitor and the fourth capacitor and between the second capacitor and the third capacitor.